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計算機結構與作業系統

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國立臺灣大學 2026 · 考試 · 第 8 題

Regarding cache conflict patterns, consider the following C code executing on a system with a 32 KB direct-mapped L1 data cache, 64-byte cache lines, and 4-byte integers.

int A[8192], B[8192];  // Arrays allocated contiguously, cache-line aligned
for (int i = 0; i < 8192; i++) {
    A[i] = A[i] + B[i];
}

Select correct description(s).

(A)
Every access to Bi results in a cache miss due to conflict with Ai.
(B)
Changing the cache to 2-way set-associative with the same total size would eliminate all conflict misses.
(C)
Adding padding of 8192 integers between arrays A and B would eliminate conflict misses.
(D)
Loop interchange would improve cache performance for this code.
(E)
Prefetching Bi+1 in each iteration would eliminate all conflict misses.

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