計算機結構與作業系統

You are analyzing a RISC-V 6-stage pipeline consisting of IF (Fetch), ID (Decode), EX (Execute), MEM1 & MEM2 (Memory), and WB (Write-Back) stages. The pipeline utilizes a split-phase register file, where writes occur in the first half of the clock cycle and reads in the second. A 2-bit branch predictor is used, and a branch instruction is resolved in the EX stage. The processor implements a branch target buffer. Therefore, when a branch is predicted "taken", the target address is also predicted. Assume this loop executes 10 iterations. Consider the following assembly code segment:

Loop:
    lw    x3, 0(x11)
    lw    x4, 0(x12)
    add   x5, x3, x4
    sw    x5, 0(x11)
    addi  x11, x11, 4
    addi  x12, x12, 4
    bne   x11, x13, Loop

The 2-bit branch predictor is a saturating counter with four states (taken arrow = branch taken, otherwise not taken):

Assume the predictor state is initialized to "Predict Non-Taken, 11", and the loop is executed multiple times. The execution cycles of an iteration are measured as the distance between the start of its instruction Fetch (IF) stage and the start of the next iteration's IF stage (or the beginning of the first instruction that exits the loop). For example, if the i-th iteration begins its IF stage at cycle 12 and the (i+1)-th iteration begins at cycle 25, the total execution time for the i-th iteration is 13 cycles. Select correct description(s).