計算機結構與作業系統(B)

(5 pts) Consider the RISC-V code below were executed concurrently on two cores.

[x2] = 1
[x3] = 1

ld   x1, 0(x2)
addi x1, x1, 1
sd   x1, 0(x2)
ld   x4, 0(x3)
add  x4, x1, x4
sd   x4, 0(x3)

Memory is shared by the two cores. Before executing the code, assuming registers x2 and x3 of each of the cores contain different values ($x2_{core0} \ne x3_{core0}$ and $x2_{core1} \ne x3_{core1}$). The same register x2 and x3 of the two cores respectively contain the same value ($x2_{core0} = x2_{core1}$ and $x3_{core0} = x3_{core1}$). The memory location x2 and x3 each contains the integer value 1 before executing the code. Assuming no instruction reordering is possible. What are all the possible values of x2 and x3 after code execution has completed?