計算機結構與作業系統(B)

(5 pts) Consider the fragment of RISC-V assembly codes below:

#1  sd  x29, 12(x16)
#2  ld  x29, 8(x16)
#3  sub x17, x29, x14
#4  add x15, x17, x14
#5  sub x15, x30, x14

Assume that we have a standard 5-stage pipeline (IF, ID, EX, MEM, WB) without data forwarding, and a register can be written and read back in the same cycle without introducing a hazard. Which CPU cycles do instruction #3 and instruction #4 complete assuming a perfect cache?