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國立政治大學 2025 · 考試 · 第 36 題

In DMA-based I/O,

(A)
CPU is relieved from data transfer and is interrupted after every word has been transferred to initiate the next word transfer.
(B)
cycle stealing can slow down the CPU computation, but off-loading the data-transfer work to a DMA controller generally improves the total system performance.
(C)
interrupt mechanism is not used.
(D)
data is transferred to/from a single block of memory, but not to/from multiple blocks.

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